Fernando Gehm Moraes

About Me

Academic Background

Ph.D. in Microelectronics, LIRMM , 1994

M.Sc. in Computer Science, PPGC‑UFRGS , 1990

B.S. in Electrical Engineering, EE‑UFRGS , 1987

Research Interests

RISC-V processors and Instruction Set Extensions (ISEs)
Microelectronics: digital ASIC design
Manycores and Networks‑on‑Chip (NoCs)
Security and reliability in embedded systems
Hardware acceleration
Rapid prototyping with FPGAs
Applications in telecommunications

Short CV

Fernando Moraes received the Electrical Engineering and M.Sc. degrees from UFRGS, Porto Alegre, Brazil, in 1987 and 1990, respectively, and the Ph.D. from LIRMM, France, in 1994 (Très Honorable avec Félicitations du Jury). He is a Full Professor at PUCRS (since 2002) and served as an Invited Professor at Université de Montpellier in 1998, 1999, 2000, and 2017. SBMICRO Financial Director for the period 2024-2026. He has authored 63 peer‑reviewed journal articles and over 280 conference papers on VLSI, many‑cores, NoCs, cryptography, and ML accelerators. He advised 35 M.Sc. and 22 Ph.D. theses. He serves on the program committees of SBCCI, ISVLSI, NoCs, and DATE, and is an Associate Editor of IEEE TCAS‑II (since 2024). Primary interests include microelectronics, FPGAs, reconfigurable architectures, security, NoCs, and MPSoCs.

Research: RISC-V, Microelectronics, NoCs, Security

News

September/25 — GAPH group at Chip in the Jungle and best paper
June/24 — Paper published at IEEE Access — Hardware Acceleration of Crystals-Kyber in Low-Complexity Embedded Systems with RISC-V Instruction Set Extensions.
November/23 — Paper published at IEEE Access — A Comprehensive Framework for Systemic Security Management in NoC-based Many-cores.
October/23 — Highlight at the XXIV PUCRS Undergraduate Research Fair: CoolChip — Gerenciamento Térmico e de Lifetime em Sistemas Manycore, student Vitor Balbinot Zanini.
October/23 — Paper published at Analog Integrated Circuits and Signal Processing — Chronos-V: a Many-core High-level Model with Support for Management Techniques.
March/23 — Paper published at Foundations and Trends® in EDA — From CNN to DNN Hardware Accelerators.
November/22 — Paper published at IEEE TCAS-II — A Comprehensive Evaluation of Convolutional Hardware Accelerators.
September/22 — Paper published at IEEE TCAS-I — A Fast, Accurate, and Comprehensive PPA Estimation of Convolutional Hardware Accelerators.
November/21 — Paper published at IEEE Access — Detection and Countermeasures of Security Attacks and Faults on NoC-based Many-Cores.
August/21 — Paper published at IEEE TCAS-I — A High-level Modeling Framework for Estimating Hardware Metrics of CNN Accelerators.
July/21 — Paper published at ACM TOCS — Modular and Distributed Management of Many-Core SoCs.
May/2021 — 25 years at PUCRS — Medalha Irmão Afonso.
March/21 — Paper published at IEEE Design & Test — Hardware Accelerator for Runtime Temperature Estimation in Many-cores.
February/21 — Paper published at IET Computers and Digital Techniques — Evaluation of the Soft Error Assessment Consistency of a JIT-based Virtual Platform Simulator.
January/21 — Papers published at IEEE Design & Test and Analog Integrated Circuits and Signal Processing.
September/20 — Paper published at IEEE Access: SDN-Based Secure Application Admission and Execution for Many-Cores. link Open Access.
June/20 — Paper published at IEEE Access: A Systemic and Secure SDN Framework for NoC-based Many-cores. link Open Access.
March/20 — Paper published at Analog Integrated Circuits and Signal Processing: System management recovery in NoC-based many-core systems. link
September/19 — SBCCI'19 Best Paper Finalist: Fine-grain Temperature Monitoring for Many-Core Systems.
August/19 — Design Automation for Embedded Systems Journal: Memphis: a Framework for Heterogeneous Many-core SoCs Generation and Validation.
May/19 — JSA and TEC Journals: The Power Impact of Hardware and Software Actuators on Self-Adaptable Many-core Systems and Self-Adaptive QoS Management at Communication and Computation Levels for Many-Core SoCs.
January/19 — JSA Journal: Hierarchical adaptive multi-objective resource management for many-core systems.
December/18 — BRAFITEC mission to France for PUCRS–Polytech Montpellier double degree.
August/18 — New papers at the SBCCI conference.
May/18 — Post-doctoral fellowship approved for Marcelo Ruaro — FAPERGS.
April/18 — Two Computer Engineering students to Montpellier via BRAFITEC: Gelmar Luiz Da Costa and Lucas Zini.
September/17 — Microelectronics Journal: BrNoC: A broadcast NoC for control messages in many-core systems.
March/17 — BRAFITEC FORCINT: Mobility project approved.
January/17 — Invited Professor in France