Demonstration README - Single Core Example

Contents:

Single core variant: generic

This demonstration shows running a simulation of a platform containing a single openCores generic processor instance, and a memory map ranging from #00000000 to #FFFFFFFF.

IMG_SINGLE_RUN

This platform can then be used to execute pre-compiled applications; the following are provided as examples:

After each application has executed, a simulation summary will be printed, indicating the number of instructions executed, and the performance of the simulation in terms of Millions of simulated Instructions executed Per Second (MIPS)

This demonstration actually runs using the Imperas Instruction Set Simulator (ISS) but a platform/module very similar to the one being used in this demonstration can be found in the Examples/SimulationControl/simplePlatformInHarnessUsingOP directory that is installed in an OVPsim or Imperas install. There is more information on the ISS below.

This example platform is written in C and is compiled with GCC under Linux or using MinGW/MSYS from http://www.mingw.org under Windows. The version of MinGW/MSYS that we use is available here.

Running the simulation

From a Microsoft window manager or Linux / MSYS shell

Launch the platform with a pre-compiled application; in Windows by double clicking one of the batch files (.bat) or in Linux / MSYS by executing one of the shell scripts (.sh).

The scripts will be available dependent upon the applications available:

The simulation will run and print statistics upon completion.

From the command line

If running a DOS command window, or a MSYS shell, or a Linux shell, simply change directory to an appropriate directory, then type the name of the ISS executable, iss.exe or issdemo.exe (dependent on installation), provide the name of the variant you want after the --variant argument, and provide the application after the --program argument, for example:

cmd > issdemo.exe --variant generic --numprocessors 1 --program ../../../Applications/peakSpeed2/peakSpeed2.OR1K-O0-g.elf

Note that often other options like --processorname and parameters such as --parameter endian=little, are also needed. Look at the above script files to see what is needed for a specific variant.

You can use issdemo.exe --help to see more options.

The simulation will run and print statistics upon completion.

Interpreting results

At the end of simulation, a number of statistics will be printed. Amongst the statistical information which is reported, are the number of 'Simulated instructions' and the 'Simulated MIPS'.

IMG_RUNOUTPUT

The 'Simulated instructions' will vary depending upon the application being executed, this count indicates the number of simulated processor instructions for the processors in the platform.

The 'Simulated MIPS' will be a measure of the number of 'Simulated instructions' over the host elapsed time. The simulation must run for around 1 second of simulated time in order to print simulated MIPS statistics.

If you have multiple processors in your simulation, there will be a statistics sections for each processor, and then a summary for the overall simulation run.

Building a Test Harness and Re-Building Applications

In order to build a full product install must have been carried out. This may be the OVP 'OVPsim' package or one of the Imperas Professional Tools packages (*SDK or *DEV).

A processor cross compiler toolchain package must be installed to allow the applications to be rebuilt.

This will be available from OVPWorld, with a package name similar to or1k.toolchain.YYYYMMDD.v.OS.exe. Alternatively an external toolchain to support this processor variant can be used. Please check the requirements.

An example of a Harness and Makefile to build it can be found in the example ../Examples/SimulationControl/simplePlatformInHarnessUsingOP/harness directory

The application ELF files used can be re-built in the applications directory.

Re-building Platform

The platform/module can be compiled using MSYS/MinGW under Windows, and GCC under Linux.

The compilation can be performed using the following command lines:

Windows Command shell
This requires an MSYS environment setup
>mingw32-make -f %IMPERAS_HOME%\ImperasLib\buildutils\Makefile.harness ^
    SRC=harness.c ^
    NOVLNV=1

Linux or Windows MSYS shell (if you have an MSYS environment set up)
>make -f ${IMPERAS_HOME}/ImperasLib/buildutils/Makefile.harness \
    SRC=harness.c \
    NOVLNV=1

Re-building Application

The applications were built using a Cross Compiler toolchain, that may be available from the OVPWorld website. An OR1K.makefile.include is included that is used to setup a basic build environment for that toolchain. This can be modified to use alternative compiler flags.

Debugging with GDB

This demo provides example scripts that allow the same simulation platform to be executed and a GDB debugger connected to the RSP port to allow the debugging of any application running on the platform.

IMG_SINGLE_DEBUG_GDB

The scripts will launch GDB in a new console window. You interact with the GDB in that console, typing 'c' to continue for example. When finished use 'quit' to exit the simulation. The following GDB debug scripts are available for this example:

The GDB is expected to be found in one of the CrossCompiler or $IMPERAS_HOME/lib/$IMPERAS_ARCH/gdb directories. If it is not available the script will fail. (See Cross Compiler Toolchains below.)

If available, a .key file gives a minimal set of commands; that, if used, will run the simulation under the debugger.

The Imperas Instruction Set Simulator (ISS)

The demonstrations provided for single core processors use the Imperas ISS to create a simple platform and run the cross compiled target applications.

The Imperas ISS is often the first simulation product used in an embedded software development project. The Imperas ISS allows the development and debug of code for the target architecture on an x86/x64 host PC with the minimum of setup and effort. It simply requires the cross compilation of your application and running the ISS with an argument to specify the name of the application object.

IMG_ISS_OVERVIEW

The ISS makes use of the Imperas OVP Fast Processor Model library providing access to over 130 different instruction accurate embedded CPU model variants from the MIPS 24Kc to the ARM Cortex-A57MPx4 quad core 64 bit processor. The ISS product package comes with all these CPU models and example usage of them.

Imperas ISS Detailed Features

For more information on the Imperas ISS, visit the ISS page on the Imperas web site.

To see the command line options available for the ISS, type 'iss.exe or issdemo.exe -help' to see a list.

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