About Me

Research Interests

  • RISC-V processors and Instruction Set Extensions (ISEs)
  • Microelectronics: digital ASIC design
  • Manycores and Networks‑on‑Chip (NoCs)
  • Security and reliability in embedded systems
  • Hardware acceleration
  • Rapid prototyping with FPGAs
  • Applications in telecommunications

Short CV

Fernando Moraes received the B.Sc. degree in electrical engineering and the M.Sc. degree from the Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, Brazil, in 1987 and 1990, respectively, and the Ph.D. degree from the Laboratoire d’Informatique, Robotique et Microélectronique de Montpellier (LIRMM), France, in 1994, with the distinction Très Honorable avec Félicitations du Jury. He has been a Full Professor at PUCRS since 2002, where he coordinated the Computer Engineering Course (2001–2006) and the Computer Science Graduate Program (2008–2010). He has advised 33 M.Sc. and 20 Ph.D. students, and co-advised 4 M.Sc. and 3 Ph.D. students. He served as Invited Professor at the Université de Montpellier in 1998, 1999, 2000, and 2017, and leads cooperation programs with French institutions, including RAISON and FORCINT. He maintains close cooperation with industry, coordinating projects with DATACOM and with EnSilica on the SoC-WiMed wireless medical-monitoring chip. He has authored or co-authored over 60 journal articles and 290 conference papers on VLSI design, covering many-cores, networks-on-chip (NoCs), RISC-V hardware acceleration, and machine-learning-driven security; one of these, "HERMES: An Infrastructure for Low Area Overhead Packet-Switching Networks on Chip", has over 800 citations. His current research interests include security and reliability in NoC-based many-cores, RISC-V instruction-set extensions for cryptography and machine learning, and hardware Trojan detection using lightweight ML models. Dr. Moraes serves on the program committees of SBCCI, ISVLSI, NOCS, and DATE, and has been an Associate Editor of the IEEE Transactions on Circuits and Systems II: Express Briefs since 2024. He is a member of SBC and SBMICRO, and a Senior Member of IEEE. [July 2026].

Open Access Papers

Research: RISC-V, Microelectronics, Manycores, NoCs, Security

Open Access Surveys

News

  • September/25 — GAPH group at Chip in the Jungle SBCCI   and best paper
  • June/24 — Paper published at IEEE AccessHardware Acceleration of Crystals-Kyber in Low-Complexity Embedded Systems with RISC-V Instruction Set Extensions.
  • November/23 — Paper published at IEEE AccessA Comprehensive Framework for Systemic Security Management in NoC-based Many-cores.
  • October/23 — Highlight at the XXIV PUCRS Undergraduate Research Fair: CoolChip — Gerenciamento Térmico e de Lifetime em Sistemas Manycore, student Vitor Balbinot Zanini. Vitor Zanini
  • October/23 — Paper published at Analog Integrated Circuits and Signal ProcessingChronos-V: a Many-core High-level Model with Support for Management Techniques.
  • March/23 — Paper published at Foundations and Trends® in EDAFrom CNN to DNN Hardware Accelerators.
  • November/22 — Paper published at IEEE TCAS-IIA Comprehensive Evaluation of Convolutional Hardware Accelerators.
  • September/22 — Paper published at IEEE TCAS-IA Fast, Accurate, and Comprehensive PPA Estimation of Convolutional Hardware Accelerators.
  • November/21 — Paper published at IEEE AccessDetection and Countermeasures of Security Attacks and Faults on NoC-based Many-Cores.
  • August/21 — Paper published at IEEE TCAS-IA High-level Modeling Framework for Estimating Hardware Metrics of CNN Accelerators.
  • July/21 — Paper published at ACM TOCSModular and Distributed Management of Many-Core SoCs.
  • May/2021 — 25 years at PUCRS — Medalha Irmão Afonso. PUCRS medal
  • March/21 — Paper published at IEEE Design & TestHardware Accelerator for Runtime Temperature Estimation in Many-cores.
  • February/21 — Paper published at IET Computers and Digital TechniquesEvaluation of the Soft Error Assessment Consistency of a JIT-based Virtual Platform Simulator.
  • January/21 — Papers published at IEEE Design & Test and Analog Integrated Circuits and Signal Processing.
  • September/20 — Paper published at IEEE Access: SDN-Based Secure Application Admission and Execution for Many-Cores. link Open Access.
  • June/20 — Paper published at IEEE Access: A Systemic and Secure SDN Framework for NoC-based Many-cores. link Open Access.
  • March/20 — Paper published at Analog Integrated Circuits and Signal Processing: System management recovery in NoC-based many-core systems. link
  • September/19 — SBCCI'19 Best Paper Finalist: Fine-grain Temperature Monitoring for Many-Core Systems.
  • August/19 — Design Automation for Embedded Systems Journal: Memphis: a Framework for Heterogeneous Many-core SoCs Generation and Validation.
  • May/19 — JSA and TEC Journals: The Power Impact of Hardware and Software Actuators on Self-Adaptable Many-core Systems and Self-Adaptive QoS Management at Communication and Computation Levels for Many-Core SoCs.
  • January/19 — JSA Journal: Hierarchical adaptive multi-objective resource management for many-core systems.
  • December/18 — BRAFITEC mission to France for PUCRS–Polytech Montpellier double degree.
  • August/18 — New papers at the SBCCI conference.
  • May/18 — Post-doctoral fellowship approved for Marcelo Ruaro — FAPERGS.
  • April/18 — Two Computer Engineering students to Montpellier via BRAFITEC: Gelmar Luiz Da Costa and Lucas Zini.
  • September/17 — Microelectronics Journal: BrNoC: A broadcast NoC for control messages in many-core systems.
  • March/17 — BRAFITEC FORCINT: Mobility project approved.
  • January/17 — Invited Professor in France
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Last update: July 9, 2026